Matthew A. Lowell




Digital Logic Implementation


Design: Verilog, VHDL

Verification: VERA, SystemVerilog

ASIC Development Methodologies, FPGA Development in Xilinx Virtex 4, Xilinx Spartan3, Altera Stratix II


CAE Tools

ASIC Tools: Synopsis VCS, Design Compiler, Physical Compiler, PrimeTime

FPGA Tools: Xilinx Foundation 7.1i, Synplicity Synplify Pro 8.3 for Xilinx FPGAs, Altera Quartus II 6.0

Familiar With: Magma BlastCreate, BlastFusion, EMA Design Automation TimingDesigner, Cadence OrCAD


Computer Languages

Proficient: C++, Perl, Tci, Matlab, Object Oriented Programming Methodologies, Makefile construction and scripting for automation

Familiar With: Java, Microsoft Visual Studio 2005, GNU Development Tools



Microsoft Word, Excel, and Visio 2003/2007

Linux (Gentoo, Redhat, and SUSE), Microsoft XP, Microsoft Windows Server 2003

Revision Control: Concurrent Versioning System, Subversion, Perforce


Supercomputer Experience

Design & documentation of 2 major digital logic components (approximately 500k gates) of a multimillion gate, high-speed 90 nm ASIC


Transitioned 100k gate, 500 MHz ASIC design to Xilinx Virtex 4 and then to Altera Stratix II FPGA, FPGA, implementation met 200 MHz target


Developed physical design flow (RTL to placed gates) for multimillion gate, high-speed 130 nm ASIC in Synopsis Design Compiler & Physical Compiler


Performed sign-off timing analysis for a multimillion gate, high-speed 130 nm ASIC using Synopsis PrimeTime.  ASIC included DDR SDRAM and HyperTransport interfaces


Specification writing, team presentations, peer reviews, team development methodologies, design reuse, and high degree of hardware-software collaboration